DFT Engineer Full Time NEW

Job Description:

About The Role

Intel’s CPU Cores Engineering organization is looking for a motivated Junior Design-for-Test (DFT) Engineer to join the ATPG team developing next-generation CPU technologies.

In this role, you will work alongside experienced engineers on the development, integration, and validation of DFT solutions for complex CPU core designs. The position provides an opportunity to gain hands-on experience with advanced semiconductor technologies, ATPG methodologies, silicon bring-up, and production test flows.

You will collaborate with teams across design, verification, validation, and manufacturing while building deep technical expertise in DFT and test methodologies.

Key Responsibilities

• Support ATPG generation, fault coverage analysis, and pattern debug activities.
• Participate in DFT integration and verification for features such as Scan, MBIST, and TAP/JTAG.
• Work with senior engineers to develop and debug manufacturing test content.
• Assist in analyzing stuck-at and transition fault coverage results.
• Contribute to RTL-level DFT implementation and validation activities.
• Develop scripts and automation tools to improve DFT workflows and debug efficiency.
• Collaborate with design, validation, and physical design teams to support project execution.
• Support silicon bring-up and post-silicon debug activities.

Qualifications

• B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or related field.
• Basic understanding of digital design fundamentals and computer architecture.
• Familiarity with Verilog/SystemVerilog and RTL concepts.
• Exposure to DFT concepts such as Scan, ATPG, MBIST, or JTAG/TAP through coursework, projects, internships, or prior experience.
• Programming or scripting experience in Python, Perl, TCL, or similar languages.
• Strong analytical and problem-solving skills.
• Good communication and teamwork abilities.
• Eagerness to learn and grow in a fast-paced engineering environment.

Preferred Qualifications

• Internship or academic project experience in VLSI, DFT, validation, or verification.
• Familiarity with Linux/Unix environments.
• Exposure to industry tools such as Tessent, VCS, Verdi, or similar EDA tools.
• Basic understanding of ATPG flows and fault models.
• Experience with scripting and automation development.
• Knowledge of semiconductor design and manufacturing flows.

What We Offer

Opportunity to work on industry-leading CPU technologies.

Mentorship from experienced DFT and silicon engineers.

Hands-on exposure to advanced semiconductor development flows.

Collaborative and technically challenging environment.

Growth opportunities in one of the industry’s most complex engineering domains.

Job Type

Experienced Hire

Shift

Shift 1 (Israel)

Primary Location:

Israel, Haifa

Additional Locations:

Business Group

Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.