Design Verification Engineer Full Time NEW

A leading defense company in Central Israel is looking for an FPGA Verification Engineer to join our team.

Responsibilities:

* Build and run advanced verification environments (System Verilog, UVM)

* Develop test plans, testbenches, and execute simulations

* Perform Functional Coverage, Constraint Random testing, UVM scoreboard and register model work

* Support legacy environments in Verilog/VHDL

* Write automation scripts in Python and TCL

Requirements:

* B.Sc. in Electrical/Electronics Engineering – mandatory

* 3+ years of experience in FPGA/ASIC verification

* Hands-on experience with UVM & System Verilog

* Proven experience in environment integration and coverage reporting

* Strong scripting skills (Python, TCL)

Advantages:

* Experience with Assertion Based Verification (ABV)

* Familiarity with Verification IPs and communication protocols (PCIe, Ethernet, I2C, SPI, AXI)

* Background in RTL design (Verilog/VHDL)